Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

A Double Node Upset Tolerant Memory Cell

As we enter the deep submicron era, the steadily shrinking feature sizes make charge sharing much easier among physically adjacent nodes in integrated circuits, which ultimately results in DNU (Double Nodes Upset). In this paper, we propose a 16-transistor memory cell. Hspice simulation shows this cell maintains its original logic status under SNU (Single Node Upset) and DNU, while DICE (Dual I...

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by p...

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when pa...

Low cost and highly reliable radiation hardened latch design in 65 nm

Intrusion-Tolerant Reliable Broadcast

We consider a system with n processes where some of them can show a byzantine behavior. A byzantine process can deviate arbitrarily from the protocol, e.g., dropping messages, changing the content of a message (different recipients may receive different content of the same broadcast message), delivering messages not sent by any process or creating fake messages. This paper introduces a new broa...